Silicon Wafers & Advanced Substrates

From 1-inch research samples to 12-inch production wafers. In stock and ready to ship.

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Available Substrates

Silicon (Si)

Available in Prime, Test, and Mechanical grades. Dopants: Boron (P-type), Phosphorus/Arsenic (N-type). Resistivity from <0.001 to >10,000 ohm-cm.

SOI (Silicon on Insulator)

Engineered for high-speed performance and low power consumption. Ideal for MEMS and RF applications.

Compound Materials

GaAs, InP, GaN: High-electron mobility substrates for optoelectronics and high-frequency communications.

Glass & Optics

Fused Silica, Quartz, Pyrex, and Borosilicate for optical windows and microfluidic applications.

Wafer Manufacturing: Tools & Processes

Understanding the provenance of your substrates is critical for device yield. The production of our single-crystal silicon involves specific thermal tools and growth methods.

1. Crystal Growth (The Czochralski Method)

Most of our Prime Grade wafers are grown using the Czochralski (CZ) process. High-purity polysilicon is melted in a quartz crucible within a specialized furnace. A seed crystal is dipped into the melt and slowly withdrawn while rotating.

This diagram illustrates how the pull rate and rotation speed control the diameter of the cylindrical ingot, ensuring a dislocation-free crystal structure.

2. Wafer Orientation and Flats

After the ingot is grown, it is ground to a precise diameter. Before slicing, "flats" or "notches" are ground into the side of the ingot. These serve as visual indicators for the crystal orientation (e.g., <100> or <111>) and doping type, which is essential for proper alignment in lithography tools.

3. Specialized Structures: SOI Wafers

For applications requiring radiation hardness or reduced parasitic capacitance, we provide Silicon-on-Insulator (SOI) wafers. These contain a buried oxide layer (BOX) sandwiched between the handle wafer and the active device layer.

Custom Fabrication Services

  • Thermal Oxidation: We use high-temperature furnaces to grow wet or dry SiO₂ layers (50nm to 2µm).
  • Wafer Thinning: Back-grinding services to achieve ultra-thin wafers (down to 5µm) for flexible electronics and TSV applications.
  • Dicing: Precision diamond sawing to cut wafers into individual chips/dies.